1. Field of the Invention
The present invention relates to an inverter circuit and more particularly, to an inverter circuit comprising an MIS (Metal Insulator Semiconductor) transistor capable of individually controlling the rising portion and falling portion of an output waveform by selectively bypassing a resistor connected to an input portion of the inverter circuit.
2. Description of the Prior Art
Conventionally, to various timing signals have been used, for example, drive each element of a dynamic random access memory (for example, a sense amplifier) or drive a sequential logic circuit precisely. In such an apparatus, in order to form a timing signal having a desired waveform for a particular application, processing such as delay is performed with respect to an input signal having a predetermined waveform. Such a waveform control apparatus includes an apparatus in which a limiter circuit is connected to an input portion of an inverter so that an output signal of the inverter is delayed. Such a circuit arrangement disclosed in Japanese Patent Laying-Open Gazette No. 293016/1986.
Furthermore, conventionally, apparatus has been used in which the values of a resistor and a capacitor, connected to an input portion or an output portion of an inverter circuit comprising an MIS transistor such as an MOS (Metal Oxide Semiconductor) transistor, are selected so that a waveform of output of the inverter is controlled. FIG. 1 is a circuit diagram showing an example thereof.
Referring to FIG. 1, a conventional inverter circuit comprising an MOS transistor comprises an input terminal A to which an input signal Vin 1 having a predetermined waveform is inputted, a CMOS (Complementary MOS) inverter 1 having a predetermined threshold value, a resistor 2 connected between a node B (a signal Vin2) corresponding to an input of the CMOS inverter 1 and the above described input terminal A, and an output terminal C from which an output signal Vout of the CMOS inverter 1 is outputted. More specifically, the CMOS inverter 1 comprises a p channel MOS transistor Q1 having a source connected to a power-supply voltage V.sub.cc, a drain connected to the output terminal C and a gate connected to the node B, and an n channel MOS transistor Q2 having a drain connected to the output terminal C, a source connected to a ground potential and a gate connected to the node B.
FIG. 2 is a waveform diagram for explaining operation of the inverter circuit shown in FIG. 1, where the axis of abscissa represents the time and the axis of ordinate represents a voltage level. In FIG. 2, a solid line A represents a voltage waveform of the signal Vin1 at the input terminal A shown in FIG. 1, a dotted line B represents a voltage waveform of the signal Vin2 at the node B shown in FIG. 1, and a dash and dot line C represents a voltage waveform of the signal Vout at the output terminal C shown in FIG. 1.
An RC circuit having a time constant determined by the resistor 2 and gate stray capacitance of the CMOS inverter 1 is formed in the input portion of the CMOS inverter 1 shown in FIG. 1. When the signal Vin1 is applied to the input terminal A, a waveform of the signal Vin2 at the point B rises and falls slowly, as represented by the dotted line B shown in FIG. 2. As a result, the signal Vout at the output terminal C has a waveform as represented by the dash and dot line C shown in FIG. 2. More specifically, as seen from comparison of the lines A and B shown in FIG. 2, the rising portion and the falling portion of the input signal become slower due to a time constant RC, so that both the falling portion and the rising portion of the output signal Vout of the CMOS inverter 1 are delayed.
FIG. 3 is a diagram showing another example of the conventional inverter, and FIG. 4 is a waveform diagram for explaining operation thereof. In FIG. 4, a solid line A represents a voltage waveform of a signal Vin at an input terminal A shown in FIG. 3, and a dash and dot line C represents a voltage waveform of a signal Vout at an output terminal C. The inverter circuit shown in FIG. 3 differs from the inverter circuit shown in FIG. 1 in that the resistor 2 is not provided. Instead, a capacitor Cl is connected between the output terminal C of the CMOS inverter 1 and a ground potential. Both the falling portion and the rising portion of a voltage Vout (represented by a dash and dot line C shown in FIG. 4) between both ends of the capacitor Cl are delayed due to discharging and charging of the capacitor Cl. As described above, in the conventional inverter circuit, the resistance value and the capacitance value in an input portion, as in FIG. 1, or an output, as in FIG. 3 portion of the CMOS inverter 1 can be suitably selected so that the rising portion and the falling portion of an output waveform are controlled, whereby a desired timing signal is obtained.
Meanwhile, in the above described inverter circuits shown in FIGS. 1 and 3, if the resistance value and the capacitance value are changed, both the rising portion and the falling portion of the output waveform are delayed, so that the rising portion and the falling portion cannot be individually controlled.
An inverter circuit for differentially delaying the rising portion and the falling portion of an output waveform has been proposed. FIG. 5 is a circuit diagram showing an example thereof, and FIG. 6 is a waveform diagram for explaining operation of the circuit shown in FIG. 5. In the inverter circuit shown in FIG. 5, an n channel MOS capacitor C2 is connected between an output terminal C of a CMOS inverter 1 and a ground potential. More specifically, the gate of the n channel MOS transistor C2 corresponds to an output portion of the n channel MOS capacitor, and the source and drain thereof corresponds to a ground portion of the n channel MOS capacitor. While a voltage more than Vth is applied to the output terminal (during time periods represented by "a" in FIG. 6), the n channel MOS capacitor C2 has capacitance. This is because a channel is formed under the gate of the n channel MOS transistor. On the other hand, while the voltage more than Vth is not applied, such a channel is not formed, so that the n channel MOS capacitor C2 does not have capacitance. More specifically, in FIG. 6, in the rising portion of an input signal Vin (represented by a solid line A), the n channel MOS capacitor C2 has capacitance depending on the output level more than Vth of the CMOS inverter 1 during the time period a, so that the falling portion of an output Vout (represented by a dash and dot line C) is substantially delayed. On the other hand, in the falling portion of the input signal Vin (represented by a solid line A), the n channel MOS capacitor C2 first does not have capacitance, so that the rising portion of the output Vout (represented by a dash and dot line C) is not so delayed. However, after the voltage at the output terminal exceeds Vth (during the time period a), the output waveform is delayed.
FIG. 7 is a diagram showing another example of an inverter circuit for differentially delaying the rising portion and the falling portion of an output waveform, and FIG. 8 is a waveform diagram for explaining operation thereof. The inverter circuit shown in FIG. 7 is the same as the inverter circuit shown in FIG. 5 except that the n channel MOS capacitor C2 shown in FIG. 5 is replaced with a p channel MOS capacitor C3. An output portion of the p channel MOS capacitor C3 is formed by to the gate of the p channel MOS transistor, and a portion maintained at a power-supply voltage V.sub.cc is formed by the source and the drain of the p channel MOS transistor. Referring to FIG. 8, during a time period represented by "b", the p channel MOS capacitor C3 has capacitance. Thus, in the rising portion of an input signal Vin (represented by a solid line A), the p channel MOS capacitor C3 first does not have capacitance, so that the falling portion of an output Vout (represented by a dash and dot line C) is not so delayed. On the other hand, in the falling portion of the input signal Vin (represented by a solid line A), the p channel MOS capacitor C3 has capacitance during the time period b, so that the rising portion of the output Vout (represented by a dash and dot line C) is substantially delayed. As described above, in the inverter circuit shown in FIGS. 5 and 7, the falling portion and the rising portion of an output waveform can be differentially delayed, respectively.
However, in the inverter circuit shown in FIGS. 5 and 7, in one of the rising portion and the falling portion of an output waveform, which is not desired to be delayed, the MOS capacitor has capacitance through a fraction of the transition period, so that some delay occurs. Such delay cannot be neglected particularly when it is desired to substantially delay the output waveform using the MOS capacitor having large capacitance.